NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!NVIDIA is looking for an expert and skilled Senior Formal Equivalence Checking and Synthesis Methodology Engineer to join our ASIC-PD Methodology team in our Bengaluru Design Centre. This team is responsible for developing, maintaining, and optimizing RTL synthesis and logic-equivalence methodologies , for our groundbreaking VLSI designs. As a member of our ASIC-PD Methodology team, we expect you to have the attitude and aptitude to define, develop, and deploy various methodologies in the RTL-Synthesis and related space. You'll be working on creating and maintaining product design methodologies, focusing on such tasks as logic-equivalence checking and RTL-synthesis, optimization and automation of work flows.What You’ll Be Doing:Develop and maintain robust equivalence checking flows (FEC/FEV) for different stages of the VLSI design cycle, including RTL-to-RTL, RTL-to-Gate, and Gate-to-Gates equivalence checking.Develop and enhance the RTL Physical-Synthesis work flows, both at full-chip and block-level.Partner with implementation teams, on both synthesis and P&R side, to understand their requirements and pain-points if any, and enhance the methodology to cover for the same.Develop and deploy various methodologies based on technology updates, design requirements, and tool-feature/version updates and bug-fixes.Finetune the recipes for designs with aggressive PPA targets while ensuring logical-equivalence is maintained.Optimize flows and methodologies for performance, capacity, and debug capabilities, ensuring efficient and effective verification of sophisticated VLSI designs.Investigate and resolve equivalence checking issues, including setup and constraint-related problems, debug failures, and performance bottlenecks.Develop custom scripts using tcl/perl/python to automate the post-processing of the reports/logs to present the results in a user-friendly format.What We Need To See:B.Tech/BS in VLSI/Electronics/Electrical Engineering or Computer Science, with 5+ years of relevant ASIC design experience and/or CAD experience, with a focus on Logic Equivalence Checking and RTL-Synthesis.Be familiar with Verilog and ASIC design flow along with experience in commercial EDA toolsStrong scripting skills in languages such as Perl, Python, and TCL.Excellent problem-solving, debugging, and analytical skills.Ability to work in a team environment and collaborate efficiently with multi-functional teams.Strong communication and documentation skillsNVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people on the planet working for us. If you're creative and autonomous, we want to hear from you!#LI-Hybrid