NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to resolve, that only we can seek, and that matter to the world. This is our life’s work to amplify human inventiveness and intelligence.NVIDIA Silicon Solutions Group seeks a versatile engineer to join a Silicon HW team. You will interpret product goals, find opportunities, and work across teams to develop and propose new power management features. Your contributions will directly impact the next generation of NVIDIA products and will span different product segments.What you’ll be doing:Develop system-level power features to address existing and new product opportunities/requirements.Understanding and optimizing DL/AI workloads on Data Center platforms.The prototype features on existing silicon/platforms, lead technical return-on-investment investigations, and design feature bring-up plans for new silicon.Analyze exciting workload profiles to identify potential opportunities.Providing input on pitfalls and opportunities during feature proposal reviews.Lead debug efforts from the HW side to root cause feature sequences bugs, silicon bugs, and sophisticated system-level issues caused by interactions between multiple HW and SW features.Work closely and proactively with other engineering teams, such as system architects, chip and board designers, software/firmware engineers, HW/SW QA teams, and Applications Engineering teams, to drive next-generation product design, development, debugging, and release.What we need to see:BS or MS degree in EE/CE or equivalent experience.Minimum of 8+ years working experience in Energy/Power Optimization, Data Centers, and ASICs.Experience in working with and optimizing Data Center systems.Experience with ASIC power-saving features, system-level power-saving features, and experience optimizing products deploying multiple ASICs with shared power constraints.Deep understanding of firmware/driver structures and their interaction with HW.Working knowledge of PVT dependencies and binning methodologies.Strong EE fundamentals, knowledgeable in digital design, computer architecture, power analysis, timing analysis, fault analysis, sampling, statistics, and scriptingEffective in a collaborative environment.NVIDIA is widely considered to be the leader of AI computing and one of the world’s most desirable employers in the technology field. We have some of the most forward-thinking and dedicated people in the world working for us. If you're creative and autonomous, we want to hear from you.Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.You will also be eligible for equity and benefits.Applications for this job will be accepted at least until October 31, 2025.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.