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Samsung Electronics logo

DFT Design Engineer -Memory Team

Samsung Electronics

DFT Design Engineer -Memory Team

Samsung Electronics logo

Samsung Electronics

full-time

Posted: November 6, 2025

Application Deadline: January 22, 2026

Job Description

Position SummaryRole and ResponsibilitiesAbout Samsung Semiconductor India Research (SSIR)With a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.As one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products. Roles and ResponsibilitiesGood Experience in Top/Block, FLAT/Hier DFT insertion flow methodologiesExecuted scan & MBIST insertion, ATPG and verification at full chip levelExperience in timing closure in DFT modes - understanding of shift, capture timing constraints, MBIST constraints and their impactsGenerate, review and validate DFT constraints to achieve timing closure of high speed designExperience in timing closure in DFT modes, RTL analysis, logic synthesis, physical design, signoff verification (STA, Formality, Simulations) Exposure to analog and mixed signal IP tests such as PLLs, MIPI etc., methods of their pattern generation and verificationExposure to post-silicon bring-up. Diagnosis and debug methods to arrive at fail points for logic or memory testsShould be able to comprehend architecture and associated limitations with respect to DFT and be able to predict the schedule, amount of task and personnel involvedUnderstanding of Power Estimation/Management for DFT modes is preferredMentor juniors, support periodic training sessions, work with teams across sites and cross-functional teams and lead by examplesStrong written and oral communication skillsExperience – 5+ YearsQualificationsB.Tech/B.E/M.Tech/M.EDisclaimerSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.Skills and Qualifications* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.

Locations

  • SSIR, Goldstone, Bangalore

Salary

Salary not disclosed

Estimated Salary Rangemedium confidence

1,500,000 - 3,500,000 INR / yearly

Source: ai estimated

* This is an estimated range based on market data and may vary based on experience and qualifications.

Skills Required

  • Top/Block DFT insertion flow methodologiesintermediate
  • FLAT/Hier DFT insertion flow methodologiesintermediate
  • Scan insertionintermediate
  • MBIST insertionintermediate
  • ATPG at full chip levelintermediate
  • DFT verification at full chip levelintermediate
  • Timing closure in DFT modesintermediate
  • Shift timing constraintsintermediate
  • Capture timing constraintsintermediate
  • MBIST constraintsintermediate
  • Generate DFT constraintsintermediate
  • Review DFT constraintsintermediate
  • Validate DFT constraintsintermediate
  • RTL analysisintermediate
  • Logic synthesisintermediate
  • Physical designintermediate
  • Signoff verification (STA, Formality, Simulations)intermediate
  • Analog and mixed signal IP tests (PLLs, MIPI)intermediate
  • Pattern generation for analog/mixed signal IPsintermediate
  • Verification of analog/mixed signal IPsintermediate
  • Post-silicon bring-upintermediate
  • Diagnosis and debug methods for logic or memory testsintermediate
  • Comprehend architecture and DFT limitationsintermediate
  • Predict schedule, task amount, and personnel involvementintermediate

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Samsung Electronics logo

DFT Design Engineer -Memory Team

Samsung Electronics

DFT Design Engineer -Memory Team

Samsung Electronics logo

Samsung Electronics

full-time

Posted: November 6, 2025

Application Deadline: January 22, 2026

Job Description

Position SummaryRole and ResponsibilitiesAbout Samsung Semiconductor India Research (SSIR)With a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.As one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products. Roles and ResponsibilitiesGood Experience in Top/Block, FLAT/Hier DFT insertion flow methodologiesExecuted scan & MBIST insertion, ATPG and verification at full chip levelExperience in timing closure in DFT modes - understanding of shift, capture timing constraints, MBIST constraints and their impactsGenerate, review and validate DFT constraints to achieve timing closure of high speed designExperience in timing closure in DFT modes, RTL analysis, logic synthesis, physical design, signoff verification (STA, Formality, Simulations) Exposure to analog and mixed signal IP tests such as PLLs, MIPI etc., methods of their pattern generation and verificationExposure to post-silicon bring-up. Diagnosis and debug methods to arrive at fail points for logic or memory testsShould be able to comprehend architecture and associated limitations with respect to DFT and be able to predict the schedule, amount of task and personnel involvedUnderstanding of Power Estimation/Management for DFT modes is preferredMentor juniors, support periodic training sessions, work with teams across sites and cross-functional teams and lead by examplesStrong written and oral communication skillsExperience – 5+ YearsQualificationsB.Tech/B.E/M.Tech/M.EDisclaimerSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.Skills and Qualifications* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.

Locations

  • SSIR, Goldstone, Bangalore

Salary

Salary not disclosed

Estimated Salary Rangemedium confidence

1,500,000 - 3,500,000 INR / yearly

Source: ai estimated

* This is an estimated range based on market data and may vary based on experience and qualifications.

Skills Required

  • Top/Block DFT insertion flow methodologiesintermediate
  • FLAT/Hier DFT insertion flow methodologiesintermediate
  • Scan insertionintermediate
  • MBIST insertionintermediate
  • ATPG at full chip levelintermediate
  • DFT verification at full chip levelintermediate
  • Timing closure in DFT modesintermediate
  • Shift timing constraintsintermediate
  • Capture timing constraintsintermediate
  • MBIST constraintsintermediate
  • Generate DFT constraintsintermediate
  • Review DFT constraintsintermediate
  • Validate DFT constraintsintermediate
  • RTL analysisintermediate
  • Logic synthesisintermediate
  • Physical designintermediate
  • Signoff verification (STA, Formality, Simulations)intermediate
  • Analog and mixed signal IP tests (PLLs, MIPI)intermediate
  • Pattern generation for analog/mixed signal IPsintermediate
  • Verification of analog/mixed signal IPsintermediate
  • Post-silicon bring-upintermediate
  • Diagnosis and debug methods for logic or memory testsintermediate
  • Comprehend architecture and DFT limitationsintermediate
  • Predict schedule, task amount, and personnel involvementintermediate

Target Your Resume for "DFT Design Engineer -Memory Team" , Samsung Electronics

Get personalized recommendations to optimize your resume specifically for DFT Design Engineer -Memory Team. Takes only 15 seconds!

AI-powered keyword optimization
Skills matching & gap analysis
Experience alignment suggestions

Check Your ATS Score for "DFT Design Engineer -Memory Team" , Samsung Electronics

Find out how well your resume matches this job's requirements. Get comprehensive analysis including ATS compatibility, keyword matching, skill gaps, and personalized recommendations.

ATS compatibility check
Keyword optimization analysis
Skill matching & gap identification
Format & readability score

Tags & Categories

India

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