Resume and JobRESUME AND JOB
Samsung Electronics logo

Lead SOC RTL Design Engineer

Samsung Electronics

Lead SOC RTL Design Engineer

Samsung Electronics logo

Samsung Electronics

part-time

Posted: November 6, 2025

Application Deadline: October 15, 2026

Job Description

Position SummaryRole and ResponsibilitiesAbout Samsung Semiconductor India Research (SSIR)With a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.As one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products. Roles and Responsibilities· 9-12 years of solid experience in SoC IP design & SoC Subsystem Designs· Experience with High Speed & Low Speed Protocol concepts· Experience with SPI/I2C/I3C/UART/PWM all Low Speed IP’s and design· Added advantage for experience in either UCIe/ Ethernet/ UFS IP’s (Host Controller, Unipro, MPHY) Architecture and protocol· Experience in managing and lead teams of 4-5 Engineers· Architectural level experienced with defining block, sub-system at SOC level· Understanding of interconnect protocols like AXI/AHB/APB concepts· Working knowledge of Lint, CDC, UPF, VCLP, DFT, Power and Clock Flow· Good understanding of the design timing closure and verification debug· Manage SoC dependencies, planning and tracking of all front-end design related tasks· Should possess effective communication and leadership skills Experience – 9 to 12 Years QualificationsB.Tech/B.E/M.Tech/M.EDisclaimerSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.Skills and Qualifications* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.

Salary

Estimated Salary Rangemedium confidence

3,500,000 - 6,000,000 INR / yearly

Source: ai estimated

* This is an estimated range based on market data and may vary based on experience and qualifications.

Skills Required

  • SoC IP designintermediate
  • SoC Subsystem Designsintermediate
  • High Speed & Low Speed Protocol conceptsintermediate
  • SPI/I2C/I3C/UART/PWM Low Speed IP’s and designintermediate
  • UCIe/ Ethernet/ UFS IP’s (Host Controller, Unipro, MPHY) Architecture and protocolintermediate
  • Managing and leading teams of 4-5 Engineersintermediate
  • Architectural level defining block, sub-system at SOC levelintermediate
  • Interconnect protocols like AXI/AHB/APB conceptsintermediate
  • Lint, CDC, UPF, VCLP, DFT, Power and Clock Flowintermediate
  • Design timing closure and verification debugintermediate
  • Managing SoC dependencies, planning and tracking of front-end design tasksintermediate
  • Effective communication and leadership skillsintermediate

Target Your Resume for "Lead SOC RTL Design Engineer" , Samsung Electronics

Get personalized recommendations to optimize your resume specifically for Lead SOC RTL Design Engineer. Takes only 15 seconds!

AI-powered keyword optimization
Skills matching & gap analysis
Experience alignment suggestions

Check Your ATS Score for "Lead SOC RTL Design Engineer" , Samsung Electronics

Find out how well your resume matches this job's requirements. Get comprehensive analysis including ATS compatibility, keyword matching, skill gaps, and personalized recommendations.

ATS compatibility check
Keyword optimization analysis
Skill matching & gap identification
Format & readability score

Related Jobs You May Like

No related jobs found at the moment.

Samsung Electronics logo

Lead SOC RTL Design Engineer

Samsung Electronics

Lead SOC RTL Design Engineer

Samsung Electronics logo

Samsung Electronics

part-time

Posted: November 6, 2025

Application Deadline: October 15, 2026

Job Description

Position SummaryRole and ResponsibilitiesAbout Samsung Semiconductor India Research (SSIR)With a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more.As one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products. Roles and Responsibilities· 9-12 years of solid experience in SoC IP design & SoC Subsystem Designs· Experience with High Speed & Low Speed Protocol concepts· Experience with SPI/I2C/I3C/UART/PWM all Low Speed IP’s and design· Added advantage for experience in either UCIe/ Ethernet/ UFS IP’s (Host Controller, Unipro, MPHY) Architecture and protocol· Experience in managing and lead teams of 4-5 Engineers· Architectural level experienced with defining block, sub-system at SOC level· Understanding of interconnect protocols like AXI/AHB/APB concepts· Working knowledge of Lint, CDC, UPF, VCLP, DFT, Power and Clock Flow· Good understanding of the design timing closure and verification debug· Manage SoC dependencies, planning and tracking of all front-end design related tasks· Should possess effective communication and leadership skills Experience – 9 to 12 Years QualificationsB.Tech/B.E/M.Tech/M.EDisclaimerSamsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.Skills and Qualifications* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.

Salary

Estimated Salary Rangemedium confidence

3,500,000 - 6,000,000 INR / yearly

Source: ai estimated

* This is an estimated range based on market data and may vary based on experience and qualifications.

Skills Required

  • SoC IP designintermediate
  • SoC Subsystem Designsintermediate
  • High Speed & Low Speed Protocol conceptsintermediate
  • SPI/I2C/I3C/UART/PWM Low Speed IP’s and designintermediate
  • UCIe/ Ethernet/ UFS IP’s (Host Controller, Unipro, MPHY) Architecture and protocolintermediate
  • Managing and leading teams of 4-5 Engineersintermediate
  • Architectural level defining block, sub-system at SOC levelintermediate
  • Interconnect protocols like AXI/AHB/APB conceptsintermediate
  • Lint, CDC, UPF, VCLP, DFT, Power and Clock Flowintermediate
  • Design timing closure and verification debugintermediate
  • Managing SoC dependencies, planning and tracking of front-end design tasksintermediate
  • Effective communication and leadership skillsintermediate

Target Your Resume for "Lead SOC RTL Design Engineer" , Samsung Electronics

Get personalized recommendations to optimize your resume specifically for Lead SOC RTL Design Engineer. Takes only 15 seconds!

AI-powered keyword optimization
Skills matching & gap analysis
Experience alignment suggestions

Check Your ATS Score for "Lead SOC RTL Design Engineer" , Samsung Electronics

Find out how well your resume matches this job's requirements. Get comprehensive analysis including ATS compatibility, keyword matching, skill gaps, and personalized recommendations.

ATS compatibility check
Keyword optimization analysis
Skill matching & gap identification
Format & readability score

Related Jobs You May Like

No related jobs found at the moment.