Resume and JobRESUME AND JOB
Samsung Electronics logo

Principal Design Verification Architect

Samsung Electronics

Principal Design Verification Architect

Samsung Electronics logo

Samsung Electronics

full-time

Posted: November 6, 2025

Application Deadline: December 31, 2025

Job Description

Position SummarySamsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!Role and ResponsibilitiesWe’re seeking a Principal Design Verification Architect to join our System IP team, where you will contribute to the functional verification of System IP, including coherent interconnect, caches, and dynamic memory controllers. As a senior-level individual contributor with technical leadership capabilities, you'll drive hands-on project execution and provide expertise in design verification. A strong background in Design Verification, test bench architecture skills, methodologies, and hands-on experience with both block-level and top-level is required to be successful in this role.You serve as the technical expert for verification know-how and micro-architectureYou design and build reusable testbenches from scratchYou identify and propose solutions to improve existing verification flowsYou architect next gen verification test benches and flows to boost productivityYou develop and implement best practices to enhance productivityYou own key features and execute tasks to meet milestonesYou create test plans, challenge specs, and review test plans/codeYou collaborate with designers to resolve spec issues and verify design correctnessYou develop verification environments, stimulus, and testsYou debug and root cause functional fails from regressionsYou analyze code and functional coverage results, performing gap analysisYou identify coverage exclusions and improve stimulusYou collaborate with SoC, Physical Design, and Performance Verification teams to debug and resolve issuesYou help with Silicon debug issuesYou provide mentorship to junior team membersSkills and Qualifications20+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 18+ years of experience with a Master’s degree, or 16+ years of experience with a PhD15+ years of industry experience in design verificationExpert-level SystemVerilog and UVM coding skillsKnowledge of ARM protocols (CHI, AXI, ACElite, APB)Experience with Git version control and Unix/Perl scriptingMust have Coherent interconnect verification experienceFamiliarity with both coherent interconnect and LPDDR memory controllers (ideal)Strong written and verbal communication skillsFormal verification skills (a plus)Our TeamOur System IP team develops proprietary coherent interconnect and memory controller deployed in many high-volume products. Our team plays a key role in influencing the product roadmap for a market-leading system IP solutions. We focus on delivering system modeling capability based on optimization and use-case-driven analysis (gaming, computational photography) that enables a world-class memory subsystem.With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.Being part of a new team of talented individuals with vastly diverse backgrounds and skill sets at a well-established global company means you have limitless room to explore, innovate, and expand role responsibilities to build technical expertise. With a big charter ahead, we get to do challenging work and solve unique problems in a highly collaborative and supportive environment. You will always be learning while helping us shape the team’s culture.Total RewardsAt Samsung – SARC/ACL, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $221,700 and $364,800. Your actual base pay will depend on variables that may include your education skills, qualifications, experience, and work location. This is an exempt position, which is not eligible for overtime pay under the Fair Labor Standards Act (FLSA).Samsung employees have access to benefits including: medical, dental, vision, life insurance, 401(k), free onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and many more. In addition, regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance.Additionally, this role might be eligible to participate in long term incentive plan and relocation.U.S. Export ControlThis position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.Trade Secrets By submitting an application, you [applicant] agree[s] not to disclose to Samsung, or induce Samsung to use, any confidential or proprietary information (including trade secrets) belonging to any current or previous employer or other person or entity.#SARC #ACL* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.* Samsung Electronics America, Inc. and its subsidiaries are committed to employing a diverse workforce, and provide Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.

Locations

  • 3900 N Capital of Texas Hwy, Austin, TX

Salary

18,401,100 - 30,278,400 INR / yearly

Estimated Salary Rangemedium confidence

18,000,000 - 36,000,000 INR / yearly

Source: ai estimated

* This is an estimated range based on market data and may vary based on experience and qualifications.

Skills Required

  • Functional verification of System IP including coherent interconnect, caches, and dynamic memory controllersintermediate
  • Hands-on project execution and technical leadershipintermediate
  • Design Verification expertiseintermediate
  • Test bench architectureintermediate
  • Verification methodologiesintermediate
  • Block-level and top-level verification experienceintermediate
  • Technical expertise in verification know-how and micro-architectureintermediate
  • Designing and building reusable testbenches from scratchintermediate
  • Identifying and proposing solutions to improve verification flowsintermediate
  • Architecting next-generation verification test benches and flowsintermediate
  • Developing and implementing best practices to enhance productivityintermediate
  • Owning key features and executing tasks to meet milestonesintermediate
  • Creating test plansintermediate
  • Challenging specificationsintermediate
  • Reviewing test plans and codeintermediate
  • Collaborating with designers to resolve spec issues and verify design correctnessintermediate
  • Developing verification environments, stimulus, and testsintermediate
  • Debugging and root causing functional fails from regressionsintermediate
  • Analyzing code and functional coverage resultsintermediate
  • Performing gap analysisintermediate
  • Identifying coverage exclusionsintermediate
  • Improving stimulusintermediate
  • Collaborating with SoC, Physical Design, and Performance Verification teamsintermediate

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Samsung Electronics logo

Principal Design Verification Architect

Samsung Electronics

Principal Design Verification Architect

Samsung Electronics logo

Samsung Electronics

full-time

Posted: November 6, 2025

Application Deadline: December 31, 2025

Job Description

Position SummarySamsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!Role and ResponsibilitiesWe’re seeking a Principal Design Verification Architect to join our System IP team, where you will contribute to the functional verification of System IP, including coherent interconnect, caches, and dynamic memory controllers. As a senior-level individual contributor with technical leadership capabilities, you'll drive hands-on project execution and provide expertise in design verification. A strong background in Design Verification, test bench architecture skills, methodologies, and hands-on experience with both block-level and top-level is required to be successful in this role.You serve as the technical expert for verification know-how and micro-architectureYou design and build reusable testbenches from scratchYou identify and propose solutions to improve existing verification flowsYou architect next gen verification test benches and flows to boost productivityYou develop and implement best practices to enhance productivityYou own key features and execute tasks to meet milestonesYou create test plans, challenge specs, and review test plans/codeYou collaborate with designers to resolve spec issues and verify design correctnessYou develop verification environments, stimulus, and testsYou debug and root cause functional fails from regressionsYou analyze code and functional coverage results, performing gap analysisYou identify coverage exclusions and improve stimulusYou collaborate with SoC, Physical Design, and Performance Verification teams to debug and resolve issuesYou help with Silicon debug issuesYou provide mentorship to junior team membersSkills and Qualifications20+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 18+ years of experience with a Master’s degree, or 16+ years of experience with a PhD15+ years of industry experience in design verificationExpert-level SystemVerilog and UVM coding skillsKnowledge of ARM protocols (CHI, AXI, ACElite, APB)Experience with Git version control and Unix/Perl scriptingMust have Coherent interconnect verification experienceFamiliarity with both coherent interconnect and LPDDR memory controllers (ideal)Strong written and verbal communication skillsFormal verification skills (a plus)Our TeamOur System IP team develops proprietary coherent interconnect and memory controller deployed in many high-volume products. Our team plays a key role in influencing the product roadmap for a market-leading system IP solutions. We focus on delivering system modeling capability based on optimization and use-case-driven analysis (gaming, computational photography) that enables a world-class memory subsystem.With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.Being part of a new team of talented individuals with vastly diverse backgrounds and skill sets at a well-established global company means you have limitless room to explore, innovate, and expand role responsibilities to build technical expertise. With a big charter ahead, we get to do challenging work and solve unique problems in a highly collaborative and supportive environment. You will always be learning while helping us shape the team’s culture.Total RewardsAt Samsung – SARC/ACL, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $221,700 and $364,800. Your actual base pay will depend on variables that may include your education skills, qualifications, experience, and work location. This is an exempt position, which is not eligible for overtime pay under the Fair Labor Standards Act (FLSA).Samsung employees have access to benefits including: medical, dental, vision, life insurance, 401(k), free onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and many more. In addition, regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance.Additionally, this role might be eligible to participate in long term incentive plan and relocation.U.S. Export ControlThis position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.Trade Secrets By submitting an application, you [applicant] agree[s] not to disclose to Samsung, or induce Samsung to use, any confidential or proprietary information (including trade secrets) belonging to any current or previous employer or other person or entity.#SARC #ACL* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.* Samsung Electronics America, Inc. and its subsidiaries are committed to employing a diverse workforce, and provide Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.

Locations

  • 3900 N Capital of Texas Hwy, Austin, TX

Salary

18,401,100 - 30,278,400 INR / yearly

Estimated Salary Rangemedium confidence

18,000,000 - 36,000,000 INR / yearly

Source: ai estimated

* This is an estimated range based on market data and may vary based on experience and qualifications.

Skills Required

  • Functional verification of System IP including coherent interconnect, caches, and dynamic memory controllersintermediate
  • Hands-on project execution and technical leadershipintermediate
  • Design Verification expertiseintermediate
  • Test bench architectureintermediate
  • Verification methodologiesintermediate
  • Block-level and top-level verification experienceintermediate
  • Technical expertise in verification know-how and micro-architectureintermediate
  • Designing and building reusable testbenches from scratchintermediate
  • Identifying and proposing solutions to improve verification flowsintermediate
  • Architecting next-generation verification test benches and flowsintermediate
  • Developing and implementing best practices to enhance productivityintermediate
  • Owning key features and executing tasks to meet milestonesintermediate
  • Creating test plansintermediate
  • Challenging specificationsintermediate
  • Reviewing test plans and codeintermediate
  • Collaborating with designers to resolve spec issues and verify design correctnessintermediate
  • Developing verification environments, stimulus, and testsintermediate
  • Debugging and root causing functional fails from regressionsintermediate
  • Analyzing code and functional coverage resultsintermediate
  • Performing gap analysisintermediate
  • Identifying coverage exclusionsintermediate
  • Improving stimulusintermediate
  • Collaborating with SoC, Physical Design, and Performance Verification teamsintermediate

Target Your Resume for "Principal Design Verification Architect" , Samsung Electronics

Get personalized recommendations to optimize your resume specifically for Principal Design Verification Architect. Takes only 15 seconds!

AI-powered keyword optimization
Skills matching & gap analysis
Experience alignment suggestions

Check Your ATS Score for "Principal Design Verification Architect" , Samsung Electronics

Find out how well your resume matches this job's requirements. Get comprehensive analysis including ATS compatibility, keyword matching, skill gaps, and personalized recommendations.

ATS compatibility check
Keyword optimization analysis
Skill matching & gap identification
Format & readability score

Tags & Categories

United States of AmericaOn-site

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