Senior Staff Analog Design
Samsung Electronics
Senior Staff Analog Design
Job Description
Position SummarySenior Analog deisgner with relevent experience of 5-12 years in Analog and Mixed Signal Design.At least Full IP design experince in one of domains as listed below.Role and Responsibilities- Low Jitter and high frequency PLL Design Experience . Both LC and Ring based PLL deisgn Experience- General Purpose ADC and thermal Senors IP deisgn Experience- High speed Serdes Design Experience.- LDO , BGR and other Power managemnt blocks.Ideal Candidate should be ready for challenging deisgn experince and exposure to silion validation . He will get full exposure to IP deisgn cycle in advanced samsung foundry process 4nm and below.Skills and QualificationsB.Tech/M.Tech / PHd* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.
Locations
- SSIR, Angkor West, Bangalore
Salary
Salary not disclosed
Estimated Salary Rangemedium confidence
2,500,000 - 4,500,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- Senior Analog Designerintermediate
- Analog and Mixed Signal Designintermediate
- Full IP Designintermediate
- Low Jitter PLL Designintermediate
- High Frequency PLL Designintermediate
- LC-based PLL Designintermediate
- Ring-based PLL Designintermediate
- General Purpose ADC Designintermediate
- Thermal Sensors IP Designintermediate
- High Speed Serdes Designintermediate
- LDO Designintermediate
- BGR Designintermediate
- Power Management Blocksintermediate
- Silicon Validationintermediate
- IP Design Cycleintermediate
- Advanced Foundry Process (4nm and below)intermediate
- B.Tech/M.Tech/PhDintermediate
Tags & Categories
Senior Staff Analog Design
Samsung Electronics
Senior Staff Analog Design
Job Description
Position SummarySenior Analog deisgner with relevent experience of 5-12 years in Analog and Mixed Signal Design.At least Full IP design experince in one of domains as listed below.Role and Responsibilities- Low Jitter and high frequency PLL Design Experience . Both LC and Ring based PLL deisgn Experience- General Purpose ADC and thermal Senors IP deisgn Experience- High speed Serdes Design Experience.- LDO , BGR and other Power managemnt blocks.Ideal Candidate should be ready for challenging deisgn experince and exposure to silion validation . He will get full exposure to IP deisgn cycle in advanced samsung foundry process 4nm and below.Skills and QualificationsB.Tech/M.Tech / PHd* Please visit Samsung membership to see Privacy Policy, which defaults according to your location. You can change Country/Language at the bottom of the page. If you are European Economic Resident, please click here.
Locations
- SSIR, Angkor West, Bangalore
Salary
Salary not disclosed
Estimated Salary Rangemedium confidence
2,500,000 - 4,500,000 INR / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- Senior Analog Designerintermediate
- Analog and Mixed Signal Designintermediate
- Full IP Designintermediate
- Low Jitter PLL Designintermediate
- High Frequency PLL Designintermediate
- LC-based PLL Designintermediate
- Ring-based PLL Designintermediate
- General Purpose ADC Designintermediate
- Thermal Sensors IP Designintermediate
- High Speed Serdes Designintermediate
- LDO Designintermediate
- BGR Designintermediate
- Power Management Blocksintermediate
- Silicon Validationintermediate
- IP Design Cycleintermediate
- Advanced Foundry Process (4nm and below)intermediate
- B.Tech/M.Tech/PhDintermediate
Tags & Categories