Digital Integrated Circuit Design Verification Engineer

Location: Vancouver, Brazil

Department: Spectacles

Employment Type: Full time

About Snap Inc

Snap Inc is a technology company. We believe the camera presents the greatest opportunity to improve the way people live and communicate. Snap contributes to human progress by empowering people to express themselves, live in the moment, learn about the world, and have fun together.

About the Role

Snap Inc is a camera company that believes the camera + AI will help people share more authentically. We’re looking for a Digital Integrated Circuit Design Verification Engineer to join our world-class Spectacles team, where we’re pioneering next-generation AR glasses that overlay computing on the real world. Our fifth-generation Spectacles, powered by Snap OS, transform how people play, learn, and work together through standalone, see-through AR. As a key member of our hardware R&D team, you’ll verify cutting-edge display ICs that bring augmented reality to life, ensuring seamless integration with Snapchat’s visual messaging and Lens Studio AR platform. In this role, you’ll collaborate with digital design, analog, software, and verification engineers to develop UVM-based testbenches and execute rigorous verification plans using Siemens Questa. You’ll tackle complex challenges in AR camera technology, driving coverage for protocols like MIPI and AMBA while automating workflows in Linux. Your work will directly contribute to pushing the boundaries of what cameras can do—empowering real-time AR experiences that connect people in the moment. We’re a creative, innovative culture that thrives on diverse backgrounds and bold ideas. The ideal candidate is a self-starter who excels in fast-paced environments, organizes intricate verification issues, and multitasks effectively. Join us in building hardware that enhances relationships, sparks creativity, and redefines human connection through AR. Snap is an equal opportunity employer committed to diversity, with a 'Default Together' policy fostering in-person collaboration 4+ days a week.

What You'll Do

• Work as part of a multi-disciplinary team designing display Integrated Circuits for AR glasses in Spectacles
• Collaborate closely with digital design, analog logic, software, and verification engineers
• Develop and implement UVM-based and assertion-based testbenches for next-generation Spectacles hardware
• Create and execute comprehensive verification test plans, including functional coverage and code coverage
• Utilize Siemens Questa tool set for advanced verification and debug tasks
• Specify, configure verification tools, and create automation scripts to streamline workflows
• Verify complex display ICs that power AR overlays on real-world camera feeds
• Drive verification efforts for Snap OS-powered fifth-generation Spectacles
• Organize complex verification issues and drive them to closure in a fast-paced AR innovation environment
• Contribute to pushing the boundaries of camera technology and augmented reality hardware

Minimum Qualifications

• BSEE or MSEE or equivalent relevant experience
• 10+ years of experience in ASIC Design Verification
• Strong knowledge of UVM and SystemVerilog for advanced verification methodologies
• Strong knowledge of digital functional simulation and tools such as Siemens Questa
• Strong knowledge of good Verilog RTL coding practices
• Excellent written and verbal English communication skills
• Experience working in Linux environment with scripting

Preferred Qualifications

• Experience with entire verification process from planning to sign-off
• Experience with Siemens’ UVM Framework
• Experience in emulation
• Experience in RTL design
• Familiarity with video and display systems, MIPI, AMBA, I2C, SPI protocols and embedded microcontroller
• Familiarity with ASIC test or production flow

Knowledge, Skills & Abilities

• UVM and SystemVerilog expertise
• Digital functional simulation
• Siemens Questa tools
• Verilog RTL coding practices
• Scripting (TCL, Make, Perl, Python, Shell)
• Linux environment proficiency
• Testbench development
• Functional and code coverage analysis
• Tool specification and automation
• Multi-disciplinary team collaboration
• Problem-solving and issue organization
• Multitasking and prioritization
• Self-starter mindset
• English communication (written and verbal)
• Understanding of AR hardware challenges
• Debugging complex IC designs

Our Benefits

• Paid parental leave
• Comprehensive medical coverage
• Emotional and mental health support programs
• Compensation packages with equity in the form of RSUs
• Competitive base salary based on pay zones (Zone A: $173,000-$259,000; Zone B: $164,000-$246,000; Zone C: $147,000-$220,000)
• "Default Together" policy with dynamic in-office collaboration 4+ days per week
• Opportunities to share in Snap’s long-term success
• Support for disabilities or special needs with accommodations

Compensation

$173,000-$259,000 annually

This position is eligible for equity in the form of RSUs.

"Default Together" Policy: At Snap Inc, we practice a "default together" approach and expect team members to work in an office 4+ days per week.

Snap is proud to be an equal opportunity employer.