芯片后端工程师
Tencent
芯片后端工程师
Job Description
芯片后端工程师
📋 Job Overview
Tencent is seeking a Backend Engineer for chip design, focusing on the physical implementation of large-scale digital chips (SoC/ASIC) from Netlist to GDSII. The role involves full-flow tasks including floorplanning, placement, routing, timing closure, power and signal integrity analysis, and physical verification. Responsibilities also include collaboration with frontend teams, process optimization, and documentation to ensure PPA goals are met.
📍 Location: Shenzhen, China
🏢 Business Unit: TEG
📄 Full Description
1.负责大规模数字芯片（SoC/ASIC）模块级或顶层级从Netlist到GDSII的全流程物理实现，包括但不限于Floorplan、Power Planning、Placement、CTS、Routing、Timing Closure等；
2.进行时序分析与收敛（STA），处理复杂时序场景（OCV, LVF, MC），并执行Timing ECO；
3.进行功耗完整性（IR/EM）和信号完整性（SI）分析及优化，确保芯片性能、功耗和面积（PPA）目标达成；
4.完成物理验证（DRC, LVS, ERC, ANT）并主导相关问题的解决；
5.与前端设计、验证团队紧密协作，参与芯片规格定义和设计优化，协助解决前后端集成问题；
6.开发或优化后端设计流程与脚本，提升设计效率和质量；
7.编写相关技术文档，支持流片（Tapout）和数据交付。
2.进行时序分析与收敛（STA），处理复杂时序场景（OCV, LVF, MC），并执行Timing ECO；
3.进行功耗完整性（IR/EM）和信号完整性（SI）分析及优化，确保芯片性能、功耗和面积（PPA）目标达成；
4.完成物理验证（DRC, LVS, ERC, ANT）并主导相关问题的解决；
5.与前端设计、验证团队紧密协作，参与芯片规格定义和设计优化，协助解决前后端集成问题；
6.开发或优化后端设计流程与脚本，提升设计效率和质量；
7.编写相关技术文档，支持流片（Tapout）和数据交付。
🎯 Key Responsibilities
- Responsible for module-level or top-level full-flow physical implementation of large-scale digital chips (SoC/ASIC) from Netlist to GDSII, including but not limited to Floorplan, Power Planning, Placement, CTS, Routing, Timing Closure, etc.
- Perform timing analysis and convergence (STA), handle complex timing scenarios (OCV, LVF, MC), and execute Timing ECO.
- Conduct power integrity (IR/EM) and signal integrity (SI) analysis and optimization to ensure chip performance, power, and area (PPA) targets are achieved.
- Complete physical verification (DRC, LVS, ERC, ANT) and lead the resolution of related issues.
- Closely collaborate with frontend design and verification teams, participate in chip specification definition and design optimization, and assist in solving frontend-backend integration issues.
- Develop or optimize backend design flows and scripts to improve design efficiency and quality.
- Write relevant technical documents, support tapeout and data delivery.
🛠️ Required Skills
- Expertise in physical design flows: Floorplan, Power Planning, Placement, CTS, Routing, Timing Closure
- Timing analysis and convergence (STA), handling OCV, LVF, MC scenarios, Timing ECO
- Power integrity (IR/EM) and signal integrity (SI) analysis and optimization
- Physical verification: DRC, LVS, ERC, ANT
- Collaboration with frontend design and verification teams
- Scripting and process development for backend design
- Technical documentation and tapeout support
Locations
- Shenzhen, China
Salary
Estimated Salary Rangemedium confidence
200,000 - 500,000 CNY / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- Expertise in physical design flows: Floorplan, Power Planning, Placement, CTS, Routing, Timing Closureintermediate
- Timing analysis and convergence (STA), handling OCV, LVF, MC scenarios, Timing ECOintermediate
- Power integrity (IR/EM) and signal integrity (SI) analysis and optimizationintermediate
- Physical verification: DRC, LVS, ERC, ANTintermediate
- Collaboration with frontend design and verification teamsintermediate
- Scripting and process development for backend designintermediate
- Technical documentation and tapeout supportintermediate
Responsibilities
- Responsible for module-level or top-level full-flow physical implementation of large-scale digital chips (SoC/ASIC) from Netlist to GDSII, including but not limited to Floorplan, Power Planning, Placement, CTS, Routing, Timing Closure, etc.
- Perform timing analysis and convergence (STA), handle complex timing scenarios (OCV, LVF, MC), and execute Timing ECO.
- Conduct power integrity (IR/EM) and signal integrity (SI) analysis and optimization to ensure chip performance, power, and area (PPA) targets are achieved.
- Complete physical verification (DRC, LVS, ERC, ANT) and lead the resolution of related issues.
- Closely collaborate with frontend design and verification teams, participate in chip specification definition and design optimization, and assist in solving frontend-backend integration issues.
- Develop or optimize backend design flows and scripts to improve design efficiency and quality.
- Write relevant technical documents, support tapeout and data delivery.
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Answer 10 quick questions to check your fit for 芯片后端工程师 @ Tencent.
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芯片后端工程师
Tencent
芯片后端工程师
Job Description
芯片后端工程师
📋 Job Overview
Tencent is seeking a Backend Engineer for chip design, focusing on the physical implementation of large-scale digital chips (SoC/ASIC) from Netlist to GDSII. The role involves full-flow tasks including floorplanning, placement, routing, timing closure, power and signal integrity analysis, and physical verification. Responsibilities also include collaboration with frontend teams, process optimization, and documentation to ensure PPA goals are met.
📍 Location: Shenzhen, China
🏢 Business Unit: TEG
📄 Full Description
1.负责大规模数字芯片（SoC/ASIC）模块级或顶层级从Netlist到GDSII的全流程物理实现，包括但不限于Floorplan、Power Planning、Placement、CTS、Routing、Timing Closure等；
2.进行时序分析与收敛（STA），处理复杂时序场景（OCV, LVF, MC），并执行Timing ECO；
3.进行功耗完整性（IR/EM）和信号完整性（SI）分析及优化，确保芯片性能、功耗和面积（PPA）目标达成；
4.完成物理验证（DRC, LVS, ERC, ANT）并主导相关问题的解决；
5.与前端设计、验证团队紧密协作，参与芯片规格定义和设计优化，协助解决前后端集成问题；
6.开发或优化后端设计流程与脚本，提升设计效率和质量；
7.编写相关技术文档，支持流片（Tapout）和数据交付。
2.进行时序分析与收敛（STA），处理复杂时序场景（OCV, LVF, MC），并执行Timing ECO；
3.进行功耗完整性（IR/EM）和信号完整性（SI）分析及优化，确保芯片性能、功耗和面积（PPA）目标达成；
4.完成物理验证（DRC, LVS, ERC, ANT）并主导相关问题的解决；
5.与前端设计、验证团队紧密协作，参与芯片规格定义和设计优化，协助解决前后端集成问题；
6.开发或优化后端设计流程与脚本，提升设计效率和质量；
7.编写相关技术文档，支持流片（Tapout）和数据交付。
🎯 Key Responsibilities
- Responsible for module-level or top-level full-flow physical implementation of large-scale digital chips (SoC/ASIC) from Netlist to GDSII, including but not limited to Floorplan, Power Planning, Placement, CTS, Routing, Timing Closure, etc.
- Perform timing analysis and convergence (STA), handle complex timing scenarios (OCV, LVF, MC), and execute Timing ECO.
- Conduct power integrity (IR/EM) and signal integrity (SI) analysis and optimization to ensure chip performance, power, and area (PPA) targets are achieved.
- Complete physical verification (DRC, LVS, ERC, ANT) and lead the resolution of related issues.
- Closely collaborate with frontend design and verification teams, participate in chip specification definition and design optimization, and assist in solving frontend-backend integration issues.
- Develop or optimize backend design flows and scripts to improve design efficiency and quality.
- Write relevant technical documents, support tapeout and data delivery.
🛠️ Required Skills
- Expertise in physical design flows: Floorplan, Power Planning, Placement, CTS, Routing, Timing Closure
- Timing analysis and convergence (STA), handling OCV, LVF, MC scenarios, Timing ECO
- Power integrity (IR/EM) and signal integrity (SI) analysis and optimization
- Physical verification: DRC, LVS, ERC, ANT
- Collaboration with frontend design and verification teams
- Scripting and process development for backend design
- Technical documentation and tapeout support
Locations
- Shenzhen, China
Salary
Estimated Salary Rangemedium confidence
200,000 - 500,000 CNY / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- Expertise in physical design flows: Floorplan, Power Planning, Placement, CTS, Routing, Timing Closureintermediate
- Timing analysis and convergence (STA), handling OCV, LVF, MC scenarios, Timing ECOintermediate
- Power integrity (IR/EM) and signal integrity (SI) analysis and optimizationintermediate
- Physical verification: DRC, LVS, ERC, ANTintermediate
- Collaboration with frontend design and verification teamsintermediate
- Scripting and process development for backend designintermediate
- Technical documentation and tapeout supportintermediate
Responsibilities
- Responsible for module-level or top-level full-flow physical implementation of large-scale digital chips (SoC/ASIC) from Netlist to GDSII, including but not limited to Floorplan, Power Planning, Placement, CTS, Routing, Timing Closure, etc.
- Perform timing analysis and convergence (STA), handle complex timing scenarios (OCV, LVF, MC), and execute Timing ECO.
- Conduct power integrity (IR/EM) and signal integrity (SI) analysis and optimization to ensure chip performance, power, and area (PPA) targets are achieved.
- Complete physical verification (DRC, LVS, ERC, ANT) and lead the resolution of related issues.
- Closely collaborate with frontend design and verification teams, participate in chip specification definition and design optimization, and assist in solving frontend-backend integration issues.
- Develop or optimize backend design flows and scripts to improve design efficiency and quality.
- Write relevant technical documents, support tapeout and data delivery.
Tags & Categories
Answer 10 quick questions to check your fit for 芯片后端工程师 @ Tencent.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs