Job Description

Locations

• PALO ALTO, California, United States

Salary

Skills Required

• DV/DFT DV experienceintermediate
• Knowledge of testability techniques and features (1149.1, 1149.6, 1687, 1500, Scan, Built-in-Self-Test, Loop-Back etc.)intermediate
• Experience in general design verification methodology, regressions, simulation, and debug toolsintermediate
• Experience with CPU/External IP taps/debug coresintermediate
• Expertise in System-Verilog/UVMintermediate
• Working knowledge of scripting languages such as TCL, python (or another scripting language such as Perl)intermediate
• Experience in triaging regressions, debugging, and resolving down to RTL or Testbench issuesintermediate

Required Qualifications

• 1+ years of DV/DFT DV experience (experience, 1 years)
• Degree in Computer Engineering or Electrical Engineering or equivalent experience (experience)
• Knowledge of testability techniques and features (1149.1, 1149.6, 1687, 1500, Scan, Built-in-Self-Test, Loop-Back etc.) covering digital logic domain, embedded memories, and PHY/IOs and JTAG/1500/1687 networks (experience)
• Experience in general design verification methodology, regressions, simulation, and debug tools (experience)
• Experience with CPU/External IP taps/debug cores (experience)
• Expertise in System-Verilog/UVM (experience)
• Working knowledge of scripting languages such as TCL, python (or another scripting language such as Perl) (experience)
• Experience in triaging regressions, debugging, and resolving down to RTL or Testbench issues (experience)

Responsibilities

• Create System Verilog/UVM test benches to verify various DFT features in RTL such as SSN, compressed and uncompressed scan, memory BIST, JTAG, and boundary scan at block and SoC-level
• Verify top-level features such as power-on self-test, clock observation, clock stop and scan dump
• Verify client-taps and assist in bring up of debug cores like ARM core sight, RISCV debug module, High Speed Phy debug modules
• Work with Emulation team in bring up and validation of DFT logic
• Run DV regressions & analyze coverage, triage & debug failures
• Run gate level simulations
• Work with the RTL designers on identifying design fixes as needed
• Work with test engineers on delivering pre-Si DV testcases for silicon bring up

Benefits

• general: Aetna PPO and HSA plans > 2 medical plan options with $0 payroll deduction
• general: Family-building, fertility, adoption and surrogacy benefits
• general: Dental (including orthodontic coverage) and vision plans, both have options with a $0 paycheck contribution
• general: Company Paid (Health Savings Account) HSA Contribution when enrolled in the High Deductible Aetna medical plan with HSA
• general: Healthcare and Dependent Care Flexible Spending Accounts (FSA)
• general: 401(k) with employer match, Employee Stock Purchase Plans, and other financial benefits
• general: Company paid Basic Life, AD&D, short-term and long-term disability insurance
• general: Employee Assistance Program
• general: Sick and Vacation time (Flex time for salary positions), and Paid Holidays
• general: Back-up childcare and parenting support resources
• general: Voluntary benefits to include: critical illness, hospital indemnity, accident insurance, theft & legal services, and pet insurance
• general: Weight Loss and Tobacco Cessation Programs
• general: Tesla Babies program
• general: Commuter benefits
• general: Employee discounts and perks program

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