SOC Design Verification Engineer, AI Hardware
Tesla
SOC Design Verification Engineer, AI Hardware
Job Description
The Self-Driving Hardware team is looking for a SOC Verification Engineer who will be responsible for pre-silicon RTL verification of block and top-level SOC. With a strong knowledge of SOC architecture and SOC verification methodologies, you will interact with multiple teams and build a metric-driven, configurable, and flexible verification environment. We are open to hiring in Austin, TX; Palo Alto, CA.
Locations
- Austin, Texas, United States
Salary
Estimated Salary Rangehigh confidence
140,000 - 220,000 USD / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- knowledge of SOC architectureintermediate
- SOC verification methodologiesintermediate
- programming skills in UVMintermediate
- programming skills in C/C++intermediate
- programming skills in Python/Perlintermediate
- verifying CPU/GPU integration at the SOC levelintermediate
- Coherency verification at the SOC levelintermediate
- Emulation experienceintermediate
- SOC bring-upintermediate
- post-silicon verificationintermediate
- Post-silicon validationintermediate
- verification experience with NOCintermediate
- verification experience with PCIeintermediate
- verification experience with Bus Fabricintermediate
- verification experience with AHBintermediate
- verification experience with AXIintermediate
- based bus architecture in UVM environmentintermediate
- UPF integrationintermediate
- boot-upintermediate
- HW/FW interaction verificationintermediate
- Reset and power verificationintermediate
- UVM based test benchesintermediate
- integrate complex multi-instance VIPsintermediate
- sub-system test benchesintermediate
- test suites at the SOC levelintermediate
- coverage driven verification plansintermediate
- High Efficiency SOC Architectureintermediate
- standard SOC peripherals and I/O (e.g. DDR, PCIe, USB)intermediate
- DMAintermediate
- memory management schemesintermediate
- multi-processor systemsintermediate
- Memory Controller Sub Systemsintermediate
- PLLintermediate
- power upintermediate
- Secured Boot schemesintermediate
Required Qualifications
- 1+ years of dedicated/hands-on DV experience (experience, 1 years)
- Strong programming skills in UVM, C/C++, Python/Perl (experience)
- Experience verifying CPU/GPU integration at the SOC level (experience)
- Coherency verification at the SOC level (experience)
- Emulation experience, working on available platforms such as Palladium, or Zebu (experience)
- Experience in SOC bring-up and post-silicon verification (experience)
- Post-silicon validation and SOC bring-up (experience)
- Hands-on verification experience with at least three of the following: NOC, PCIe, Bus Fabric, AHB, AXI, based bus architecture in UVM environment (experience)
- Experience working on UPF integration, boot-up, HW/FW interaction verification (experience)
- Reset and power verification (experience)
Responsibilities
- Work with team members to define and set up a SOC-level verification environment
- Architect highly reusable UVM based test benches and integrate complex multi-instance VIPs, sub-system test benches, and test suites at the SOC level
- Achieve targeted coverage and work with Design, Architecture, SW, FW and external IP delivery teams to efficiently integrate and verify the design
- Create coverage driven verification plans from specifications
- Execute, review, and refine to achieve coverage targets
- Define and review verification and validation test plans created by other members of the team
- Post-silicon validation and SOC bring-up
Benefits
- general: Aetna PPO and HSA plans > 2 medical plan options with $0 payroll deduction
- general: Family-building, fertility, adoption and surrogacy benefits
- general: Dental (including orthodontic coverage) and vision plans, both have options with a $0 paycheck contribution
- general: Company Paid (Health Savings Account) HSA Contribution when enrolled in the High Deductible Aetna medical plan with HSA
- general: Healthcare and Dependent Care Flexible Spending Accounts (FSA)
- general: 401(k) with employer match, Employee Stock Purchase Plans, and other financial benefits
- general: Company paid Basic Life, AD&D, short-term and long-term disability insurance
- general: Employee Assistance Program
- general: Sick and Vacation time (Flex time for salary positions), and Paid Holidays
- general: Back-up childcare and parenting support resources
- general: Voluntary benefits to include: critical illness, hospital indemnity, accident insurance, theft & legal services, and pet insurance
- general: Weight Loss and Tobacco Cessation Programs
- general: Tesla Babies program
- general: Commuter benefits
- general: Employee discounts and perks program
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Answer 10 quick questions to check your fit for SOC Design Verification Engineer, AI Hardware @ Tesla.
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SOC Design Verification Engineer, AI Hardware
Tesla
SOC Design Verification Engineer, AI Hardware
Job Description
The Self-Driving Hardware team is looking for a SOC Verification Engineer who will be responsible for pre-silicon RTL verification of block and top-level SOC. With a strong knowledge of SOC architecture and SOC verification methodologies, you will interact with multiple teams and build a metric-driven, configurable, and flexible verification environment. We are open to hiring in Austin, TX; Palo Alto, CA.
Locations
- Austin, Texas, United States
Salary
Estimated Salary Rangehigh confidence
140,000 - 220,000 USD / yearly
Source: ai estimated
* This is an estimated range based on market data and may vary based on experience and qualifications.
Skills Required
- knowledge of SOC architectureintermediate
- SOC verification methodologiesintermediate
- programming skills in UVMintermediate
- programming skills in C/C++intermediate
- programming skills in Python/Perlintermediate
- verifying CPU/GPU integration at the SOC levelintermediate
- Coherency verification at the SOC levelintermediate
- Emulation experienceintermediate
- SOC bring-upintermediate
- post-silicon verificationintermediate
- Post-silicon validationintermediate
- verification experience with NOCintermediate
- verification experience with PCIeintermediate
- verification experience with Bus Fabricintermediate
- verification experience with AHBintermediate
- verification experience with AXIintermediate
- based bus architecture in UVM environmentintermediate
- UPF integrationintermediate
- boot-upintermediate
- HW/FW interaction verificationintermediate
- Reset and power verificationintermediate
- UVM based test benchesintermediate
- integrate complex multi-instance VIPsintermediate
- sub-system test benchesintermediate
- test suites at the SOC levelintermediate
- coverage driven verification plansintermediate
- High Efficiency SOC Architectureintermediate
- standard SOC peripherals and I/O (e.g. DDR, PCIe, USB)intermediate
- DMAintermediate
- memory management schemesintermediate
- multi-processor systemsintermediate
- Memory Controller Sub Systemsintermediate
- PLLintermediate
- power upintermediate
- Secured Boot schemesintermediate
Required Qualifications
- 1+ years of dedicated/hands-on DV experience (experience, 1 years)
- Strong programming skills in UVM, C/C++, Python/Perl (experience)
- Experience verifying CPU/GPU integration at the SOC level (experience)
- Coherency verification at the SOC level (experience)
- Emulation experience, working on available platforms such as Palladium, or Zebu (experience)
- Experience in SOC bring-up and post-silicon verification (experience)
- Post-silicon validation and SOC bring-up (experience)
- Hands-on verification experience with at least three of the following: NOC, PCIe, Bus Fabric, AHB, AXI, based bus architecture in UVM environment (experience)
- Experience working on UPF integration, boot-up, HW/FW interaction verification (experience)
- Reset and power verification (experience)
Responsibilities
- Work with team members to define and set up a SOC-level verification environment
- Architect highly reusable UVM based test benches and integrate complex multi-instance VIPs, sub-system test benches, and test suites at the SOC level
- Achieve targeted coverage and work with Design, Architecture, SW, FW and external IP delivery teams to efficiently integrate and verify the design
- Create coverage driven verification plans from specifications
- Execute, review, and refine to achieve coverage targets
- Define and review verification and validation test plans created by other members of the team
- Post-silicon validation and SOC bring-up
Benefits
- general: Aetna PPO and HSA plans > 2 medical plan options with $0 payroll deduction
- general: Family-building, fertility, adoption and surrogacy benefits
- general: Dental (including orthodontic coverage) and vision plans, both have options with a $0 paycheck contribution
- general: Company Paid (Health Savings Account) HSA Contribution when enrolled in the High Deductible Aetna medical plan with HSA
- general: Healthcare and Dependent Care Flexible Spending Accounts (FSA)
- general: 401(k) with employer match, Employee Stock Purchase Plans, and other financial benefits
- general: Company paid Basic Life, AD&D, short-term and long-term disability insurance
- general: Employee Assistance Program
- general: Sick and Vacation time (Flex time for salary positions), and Paid Holidays
- general: Back-up childcare and parenting support resources
- general: Voluntary benefits to include: critical illness, hospital indemnity, accident insurance, theft & legal services, and pet insurance
- general: Weight Loss and Tobacco Cessation Programs
- general: Tesla Babies program
- general: Commuter benefits
- general: Employee discounts and perks program
Tags & Categories
Answer 10 quick questions to check your fit for SOC Design Verification Engineer, AI Hardware @ Tesla.
10 Questions
~2 Minutes
Instant Score
Related Books and Jobs